This invention relates to a voltage comparator circuit which is useful when utilized in A/D converters as well as D/A converters.
Voltage comparator circuits are well known in the art. They are disclosed in, e.g., "Monolithic Expandable 6 Bit 20 MHz CMOS/SOS A/D Converter" in Journal of S.S.C. of IEEE, 1979, Vol. SC-14, and U.S. Pat. No. 3,676,702 to McGrogan, Jr. entitled "Comparator Circuit".
One example of a known voltage comparator circuit will be explained with reference to FIG. 1 through FIG. 5.
FIG. 1 is a circuit diagram of a conventional voltage comparator circuit. FIG. 2 shows the waveforms of clock signals .phi..sub.1 and .phi..sub.2 for controlling the circuit shown in FIG. 1. In the circuit, when the clock signals .phi..sub.1 and .phi..sub.2 are supplied to a transfer gate, or transistor switching circuit, 1, the switching circuit 1 is conducting if the clock signals .phi..sub.1 and .phi..sub.2 have logic levels "0+ (-V.sub.SS) and "1" (=V.sub.DD), respectively. An input signal V.sub.in2 being supplied to the switching circuit 1 is then transferred to a node 2. Hence, voltage V.sub.C at the node 2 rises to the voltage of the input signal V.sub.in2 ; V.sub.C =V.sub.in2. The switching circuit 1 is comprised of an N-channel MOS transistor and a P-channel MOS transistor. At the same time, when the clock signals .phi..sub.1 and .phi..sub.2 are supplied to a witching circuit 4, the switching circuit is conducting accordingly. The output voltage V.sub.out from an amplifier 6 is fed back to a node 5.
The amplifier 6 has input/output transfer characteristics as illustrated in FIG. 3, wherein the input voltage V.sub.i and output voltage V.sub.out are plotted on an abscissa and an ordinate, respectively. In FIG. 3, curve A represents the input/output transfer characteristics of the amplifier 6, and line B denotes the DC feedback characteristic which the amplifier 6 exhibits when its input/output terminals are short-circuited. A potential V.sub.i at the node 5 shown in FIG. 1 is therefore defined by the intersection of curve A and line B; V.sub.i =V.sub.op =V.sub.out. The input voltage V.sub.i for the amplifier 6 which is equal to V.sub.op will hereinafter be referred to as the "voltage of operating point".
When the clock signals .phi..sub.1 and .phi..sub.2 have logic levels "1" (+V.sub.DD) and "0" (-V.sub.SS), respectively, both the switching circuits 1 and 4 are non-conducting and a switching circuit 8 is conducting. An input voltage V.sub.inl is then applied to the node 2 and voltage V.sub.C at the node 2 changes to V.sub.in1. The potential difference, or the voltage between the ends of a capacitor 10 remains unchanged because the charge stored in the capacitor 10 is constant. As a result, the potential V.sub.i at the node 5 changes by the difference voltage at the node 2, i.e. (V.sub.in1 -V.sub.in2). Therefore, the potential V.sub.i at the node 5 is given as follows: EQU V.sub.i =(V.sub.in1 -V.sub.in2)+V.sub.op.
The output voltage V.sub.out of the amplifier 6 is expressed by the following equation, where K is the gain of the amplifier 6 (K&lt;0): EQU V.sub.out =K(V.sub.in1 -V.sub.in2)+V.sub.op ( 1)
In other words, the output voltage V.sub.out is obtained from the amplifier 6 by amplifying the difference voltage between voltages V.sub.in1 and V.sub.in2.
FIGS. 4 and 5 show the waveforms representing the output from the voltage comparator circuit of FIG. 1. FIGS. 4 and 5 each show not only the waveform "L" of the clock signal .phi..sub.1 but also the waveform "H" of an ideal output from the amplifier. The "ideal output" is represented by an ideal curve I which satisfies equation (1). As shown in FIGS. 4 and 5, the output voltage V.sub.out is set to V.sub.op whenever the level of the clock signal .phi..sub.1 falls to logical "0" level. Therefore, the output voltage V.sub.out will have an ideal curve I if the clock signal .phi..sub.1 has a relatively low frequency, as illustrated in FIG. 4. The negative going edge of the output waveform H can sufficiently return to the voltage V.sub.op, resulting in satisfactory voltage comparison. Conversely, if the clock signal .phi..sub.1 has a relatively high frequency, as shown in FIG. 5, the output voltage V.sub.out will not have the ideal curve I. In other words, in a lower frequency range the output voltage of the amplifier 6 can trace the rising and falling edges of the input voltage to the amplifier 6, but in a higher frequency range it cannot. Therefore, the maximum sampling frequency used in voltage comparison is limited. It should be noted that the frequency of a sampling clock signal .phi..sub.1 shown in FIG. 5 is twice as high as that of the sampling clock signal .phi..sub.1 shown in FIG. 4, and the overall period of the sampling pulse .phi..sub.1 in FIG. 5 is equal to approximately a half period of that in FIG. 4.
Although not shown in FIG. 1, the amplifier 6 is of the type which has a large capacitance at its output. Hence, the low frequency output signal from the amplifier 6 has a rise time long enough to achieve a satisfactory voltage comparison. In contrast, the polarity of the high frequency output signal may be inverted before it reaches a predetermined peak value, inevitably resulting in an inaccurate voltage comparison.
In the conventional circuit of FIG. 1, the low frequency voltage gain of the amplifier 6 varies according to a high sampling frequency. If the amplifier 6 is to have a gain large enough to achieve a satisfactory voltage comparison, the upper limit of its frequency band must be raised to about the level of the sampling frequency.